i work where models meet silicon: computer architecture, inference systems, and the verification that keeps chips honest.
senior in ece at princeton, minoring in cs + english. co-founder @ murphy labs, where we break robots before the real world does.
aarushgoradia.com · linkedin · letterboxd
senior thesis: trillion-param moe inference on commodity hardware. the whole model sits in nvme nand, and the active experts get staged through dram into gpu memory. my bandwidth model says sequential decode is stuck around 1.5 tok/s on our hardware, so i'm modifying llama.cpp to get past 10 tok/s. advised by david wentzlaff.
veri2: co-first author. rtl→sva training data filtered by jaspergold proofs, then qwen2.5-coder-7b fine-tuned on it. 50.2% formal yield vs gpt-5's 41.4%. planning to put it on arxiv.
- riscv-branch-predictors: bimodal, gshare and tage-lite on a 5-stage rv32im pipeline. gshare cut nested-loop mispredicts from 90.6% to 3.8%, but decode-stage redirects ate most of the ipc win.
- riscv-pipelined-core: 5-stage rv32i in systemverilog: forwarding, load-use interlock, branch flush.
- llm-wiki: my research wiki for comp arch + inference papers. claude code writes the linked pages, i write the takes.
- slam-rc-car: ros 2 rc car that maps a room with lidar + imu and drives an apriltag route on its own.
qualcomm (formal + uvm for noc power management) · advanced micro foundry (gds fab checks + drc for tape-out) · princeton rover (electrical) · ai seer (llm fact-checking, us patent filed)
tools: systemverilog, verilog, c++, c, python · jaspergold, uvm, verilator, vivado, cadence virtuoso, klayout, kicad